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? semiconductor components industries, llc, 2013 june, 2013 ? rev. 3 1 publication order number: ncv7608/d ncv7608 octal configurable low/high side driver the ncv7608 integrates 8 output drivers configurable in any combination of high ? side, low ? side, or h ? bridge configurations. the integrated standard serial peripheral interface (spi) allows digital control of all output stages and provides diagnostic fault information. in addition, four channels (#5 ? 8) can be pwm controlled via external control input pins. integrated clamping circuits (both in high and low ? side operational modes), waveshaping, positive and negative transient protection, and dedicated channel pair overtemperature shutdown circuits provide for a wide range of automotive and industrial applications. features ? eight independent configurable drivers ? r ds(on) = 1.2 (typ @25 c) ? spi interface for data communication ? 16 bit frame length, daisy chain compatible ? 3.3 v/5 v compatible ? frame detection ? pwm inputs for 4 outputs ? ultra ? low standby current ? over current protection ? characterized to aec q10x ? 12 ? rev a ? high ? side and low ? side flyback protection ? fault repoting ? undervoltage lockout (vs and v cc ) ? overvoltage shutdown (vs) ? supports led loads ? supports cold cranking operation down to 3 v ? overtemperature protection ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable ? these are pb ? free devices typical applications ? automotive ? industrial ? relay drive ? dc motor drive ? led drive a = assembly location wl = wafer lot yy = year ww = work week g or = pb ? free package marking diagrams soic ? 28 dw suffix case 751f http://onsemi.com ncv7608 awlyywwg see detailed ordering and shipping information in the package dimensions section on page 25 of this data sheet. ordering information ssop36 ep dq suffix case 940ab ncv7608 awlyyww (note: microdot may be in either location)
ncv7608 http://onsemi.com 2 d5 s5 d8 s8 d4 s4 spi in5 in8 vcc csb sclk si so vs gnd d1 s1 bias + supply monitoring in6 in7 en figure 1. block diagram (see figure 2 for detailed diagram)
ncv7608 http://onsemi.com 3 d5..8 s5..8 in5 in6 vcc csb sclk si so en vs gnd core functions + supply monitoring overtemp overcurrent fault gate drive control d1..4 s1..4 overtemp overcurrent open load fault gate drive control open load in7 in8 charge pump charge pump vs overtemp channels 1&2 overtemp channels 3&4 overtemp channels 5&6 overtemp channels 7&8 channels 5-8 channels 1-4 to channels 5-8 waveshaping slew rate control waveshaping slew rate control figure 2. detailed block diagram
ncv7608 http://onsemi.com 4 figure 3. pin connections 1 d2 s2 s1 d1 csb sclk d3 s3 s4 d4 vs in8 in7 in6 in5 en d8 s8 s7 d7 si vcc so gnd d5 s5 s6 d6 d2 s2 s1 d1 nc csb sclk si nc nc vcc so gnd nc d5 s5 s6 d6 d3 s3 s4 d4 vs nc in8 in7 nc nc in6 in5 en nc d8 s8 s7 d7 soic ? 28 ssop36 1 soic ? 28 package pin description pin # symbol description 1 d2 drain of configurable driver #2 2 s2 source of configurable driver #2 3 s1 source of configurable driver #1 4 d1 drain of configurable driver #1 5 csb spi chip select ?bar? (100 k pullup resistor to v cc ) 6 sclk spi clock (100 k pulldown resistor) 7 si spi serial data input (100 k pulldown resistor) 8 vcc logic supply input voltage 9 so spi serial data output 10 gnd ground ? device substrate 11 d5 drain of configurable driver #5 12 s5 source of configurable driver #5 13 s6 source of configurable driver #6 14 d6 drain of configurable driver #6 15 d7 drain of configurable driver #7 16 s7 source of configurable driver #7 17 s8 source of configurable driver #8 18 d8 drain of configurable driver #8 19 en global enable (active high) (1 00 k pulldown resistor) 20 in5 pwm control input for driver #5, (active high) (100 k pulldown resistor) ground if not used. 21 in6 pwm control input for driver #6, (active high) (100 k pulldown resistor) ground if not used. 22 in7 pwm control input for driver #7, (active high) (100 k pulldown resistor) ground if not used. 23 in8 pwm control input for driver #8, (active high) (100 k pulldown resistor) ground if not used. 24 vs battery supply input voltage. 25 d4 drain of configurable driver #4 26 s4 source of configurable driver #4 27 s3 source of configurable driver #3 28 d3 drain of configurable driver #3
ncv7608 http://onsemi.com 5 ssop36ep package pin description pin # symbol description 1 d2 drain of configurable driver #2 2 s2 source of configurable driver #2 3 s1 source of configurable driver #1 4 d1 drain of configurable driver #1 5 nc no connection. this pin should be isolated from any traces or via on the pcb board. 6 csb spi chip select ?bar? (100k pullup resistor to vcc) 7 sclk spi clock (100k pulldown resistor) 8 si spi serial data input (100k pulldown resistor) 9 nc no connection. this pin should be isolated from any traces or via on the pcb board. 10 nc no connection. this pin should be isolated from any traces or via on the pcb board. 11 vcc logic supply input voltage 12 so spi serial data output 13 gnd ground ? device substrate 14 nc no connection. this pin should be isolated from any traces or via on the pcb board. 15 d5 drain of configurable driver #5 16 s5 source of configurable driver #5 17 s6 source of configurable driver #6 18 d6 drain of configurable driver #6 19 d7 drain of configurable driver #7 20 s7 source of configurable driver #7 21 s8 source of configurable driver #8 22 d8 drain of configurable driver #8 23 nc no connection. this pin should be isolated from any traces or via on the pcb board. 24 en global enable (active high) (100k pulldown resistor) 25 in5 pwm control input for driver #5, (active high) (100k pulldown resistor) ground if not used. 26 in6 pwm control input for driver #6, (active high) (100k pulldown resistor) ground if not used. 27 nc no connection. this pin should be isolated from any traces or via on the pcb board. 28 nc no connection. this pin should be isolated from any traces or via on the pcb board. 29 in7 pwm control input for driver #7, (active high) (100k pulldown resistor) ground if not used. 30 in8 pwm control input for driver #8, (active high) (100k pulldown resistor) ground if not used. 31 nc no connection. this pin should be isolated from any traces or via on the pcb board. 32 vs battery supply input voltage. 33 d4 drain of configurable driver #4 34 s4 source of configurable driver #4 35 s3 source of configurable driver #3 36 d3 drain of configurable driver #3
ncv7608 http://onsemi.com 6 maximum ratings (voltages are with respect to device substrate) rating symbol value unit digital supply input voltage (v cc ) vccmax ? 0.3 to 7 v battery supply input voltage (vs) dc input supply voltage transient input supply voltage vsdcmax vsacmax ? 0.3 to 34 ? 0.3 to 40 v v digital i/o pin voltage (in5, in6, in7, in8, si, so, csb, sclk, en) viomax ? 0.3 to 7 v configured for high ? side operation drain = vs source output dc voltage (s1 ? s8) transient source output voltage (s1 ? s8) vshsxdcmax vshsxacmax ? 1 to 34 ? 29 to 34 v v configured for low ? side operation source = gnd drain output dc voltage (d1 ? d8) transient drain output voltage (d1 ? d8) vdlsxdcmax vdlsxacmax ? 1 to 34 (note 1) ? 1 to 48 (note 2) v v clamping energy maximum (single pulse) repetitive (multiple pulse) (note )3 wmax wrep 100 20 mj mj electrostatic discharge (vs, d1 ? d8, s1 ? s8) human body model (100 pf, 1.5 k ) machine model (200 pf) charged device esd4 ? 4000 to 4000 ? 200 to 200 ? 1000 to 1000 v electrostatic discharge (all other pins) human body model (100 pf, 1.5 k ) machine model (200pf) charged device esd2 ? 2000 to 2000 ? 200 to 200 ? 1000 to 1000 v aecq10x ? 12 ? reva short ? circuit reliability characterization aecsc grade b storage temperature range tstr ? 55 to 150 c moisture sensitivity level so28 ssop36 ? epad mslso mslssop msl3 msl2 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. in this configuration lower voltage limit is due to drain ? gate clamp. 2. internally limited. 3. 1638000 pulses (triangular), 350 ma peak, vs = 18 v, 47 , 410 mh, t a = 85 c. recommended operating conditions rating symbol value unit min max digital supply input voltage (v cc ) vccop 3.15 5.25 v battery supply input voltage (vs) vsop 5 . 5 28 v dc output current (sx,dx) ixop ? 350 ma junction temperature t j ? 40 150 c thermal conditions thermal parameter (note 4) value unit junction ? to ? lead ( jl ) so28 ssop36 ? ep 34 37 c/w junction ? to ? ambient (r ja ) so28 ssop36 ? ep 64.6 55.8 c/w junction ? to ? exposed ? pad ( jpad ) ssop36 ? ep 7.3 c/w 4. pcb 50x50x1.2 mm fr4, 2s0p, 2 oz copper, 650 sq mm heater spreader area with no vias. all 8 channels are dissipating 0.147 wa tts of power each.
ncv7608 http://onsemi.com 7 electrical characteristics ( ? 40 c < t j < 150 c, 5.5 v < vs < 28 v, 3.15 v < v cc < 5.25 v, en = v cc , unless otherwise specified) characteristic symbol conditions min typ max unit general parameters vs supply current standby (note 5) run (note 6) iqvs85 ivsop en = 0 v, 0 v v cc 5.25 v, dx = vs = 13.2 v, sx = 0 v, ? 40 c < t j < 85 c all channels active 0 ? 1 ? 5 12 a ma vcc supply current standby (note 7) run iqvcc ivccop en = 0 v, csb = v cc , ? 40 c < t j < 85 c all channels active, i (so) = 0 0 ? 1 ? 5 3 a ma vcc power ? on reset threshold vccpor v cc increasing 2.6 2.8 3.0 v vcc power ? on reset hysteresis vcchys 100 200 ? mv vs undervoltage threshold vsuv vs increasing 2.5 2.8 3.0 v vs undervoltage hysteresis vsuhys 100 200 ? mv vs overvoltage threshold vsov vs increasing 32 36 40 v vs overvoltage hysteresis vsohys 1.0 2.5 4.0 v thermal response thermal warning tw not ate tested 120 145 170 c thermal warning hysteresis twh not ate tested ? 30 ? c overtemperature shutdown tlim not ate tested 155 175 195 c overtemperature shutdown hysteresis tlimhy not ate tested ? 30 ? c ratio of overtemperature shutdown to thermal warning tstotw not ate tested 1.05 1.20 ? c/ c power outputs, dc characteristics output transistor r ds(on) (note 8) ronopx ronvsminx ronvs3 vs = 8 v, i(dx) = 200 ma vs = 5.5 v, i(dx) = 200 ma vs = 3 v, i(dx) = 200 ma ? ? ? 1.2 1.4 1.6 2.8 5.6 9.9 output leakage current (note 9) ilkgx vs = dx = 16 v, sx = 0 v ? ? 5 a open load diagnostic sink current low side idiaglsx dx = 2.6 v, sx = 0 v, output disabled 1 00 215 35 0 a open load diagnostic source current high side (note 10) idiaghsx dx = vs, sx = vs ? 2.6 v, output disabled ? 40 c < t j < 125 c ? 500 ? 330 ? 150 a open load detection threshold voltage, vd (ls) voldx 1.0 2.0 3.0 v open load detection threshold voltage, vs (hs) volsx vs ? 3 vs ? 2 vs ? 1 v over current (note 11) high ? side low ? side ilimhs ilimls vs = 16 v vs = 16 v ? 1.90 0.80 ? 1.35 1.35 ? 0.80 1.90 a output fault filter time over current open load tfoc tfol 50 50 100 100 200 200 s 5. refer to figures 13 and 18 for the vs standby current behavior. 6. refer to figure 11. i(vs) versus temperature. 7. refer to figure 17 for the v cc standby current behavior. 8. refer to figures 12 and 15 for r ds(on) behavior. 9. refer to figure 16 for output leakage current behavior. 10. refer to figures 19 and 20 for open load diagnostic current behavior. 11. refer to figure 14 for current limit behavior.
ncv7608 http://onsemi.com 8 electrical characteristics ( ? 40 c < t j < 150 c, 5.5 v < vs < 28 v, 3.15 v < v cc < 5.25 v, en = v cc , unless otherwise specified) characteristic unit max typ min conditions symbol output clamps output clamp voltage drain with respect to source vocls i(dx) = 50 ma source = gnd 34 ? 48 v output clamp voltage source with respect to gnd vochs i(sx) = ? 50 ma, vs = 14 v ? 29 ? 22 ? 16 v power outputs, ac characteristics low side rise time t_lsr 8 v < vs < 16 v r load = 70 10/90% criteria, figure 5 ? 12 50 s low side fall time t_lsf 8 v < vs < 16 v r load = 70 10/90% criteria, figure 4 ? 12 50 s high side rise time t_hsr 8 v < vs < 16 v r load = 70 10/90% criteria, figure 4 ? 12 50 s high side fall time t_hsf 8 v < vs < 16 v r load = 70 10/90% criteria, figure 5 ? 12 50 s serial control output turn ? on time (high side and low ? side configuration) tdons 8 v < vs < 16 v csb going high (at 90%) to v final going high (at 10%) or v final going low (at 90%) r load = 70 , figure 4 1 ? 50 s serial control output turn ? off time (high side and low ? side configuration) tdoffs 8 v < vs < 16 v csb going high (at 90%) to v final going low (at 90%) or v final going high (at 10%) r load = 70 , figure 5 1 ? 100 s parallel control output turn ? on time (high side and low ? side configuration) tdonp 8 v < vs < 16 v inx going high (at 90%) to v final going high (at 10%) or v final going low (at 90%) r load = 70 , figure 6 1 ? 50 s parallel control output turn ? off time (high side and low ? side configuration) tdoffp 8 v < vs < 16 v inx going low (at 10%) to v final going low (at 90%) or v final going high (at 10%) r load = 70 , figure 7 1 ? 100 s
ncv7608 http://onsemi.com 9 csb high ? side low ? side figure 4. serial turn on csb high ? side low ? side figure 5. serial turn off inx high ? side low ? side figure 6. parallel turn on inx high ? side low ? side figure 7. parallel turn off end inx en hs ls figure 8. en delay time spiwak csb sclk 10 mhz so en figure 9. spi wake up t_hsr t_lsf tdons tdoffs t_hsf t_lsr tdonp tdoffp t_hsf
ncv7608 http://onsemi.com 10 table 1. digital interface characteristics characteristic symbol conditions min typ max unit digital input high threshold vinh 2.0 ? ? v digital input low threshold vinl ? ? 0.6 v input pulldown resistance (en, si, sclk, in5, in6, in7, in8) rpdx en = si = sclk = v cc , in5 = in6 = in7 = in8 = v cc 50 100 200 k input pullup resistance (csb) ipucsb csb = 0 v 50 100 200 k csb leakage to v cc ilcsx csb = 5 v, v cc = 0 v ? ? 10 a input capacitance (note 12) cinx not ate tested ? ? 15 pf so ? output high vouth i(out) = ? 1 ma v cc ? 1.0 ? ? v so ? output low voutl i(out) = 1.6 ma ? ? 0.4 v so tristate leakage ilsox csb = v cc ? 10 ? 10 a so tristate input capacitance (note 12) csox not ate tested ? ? 15 pf sclk frequency clkf v cc = 5 v v cc = 3.3 v ? ? ? ? 5 2 mhz sclk clock period clkper v cc = 5 v v cc = 3.3 v 200 500 ? ? ? ? ns ns sclk high time clkh v cc = 5 v, figure 10 85 ? ? ns sclk low time clkl v cc = 5 v, figure 10 85 ? ? ns sclk setup time clksup v cc = 5 v, figure 10 85 ? ? ns si setup time sisup v cc = 5 v, figure 10 50 ? ? ns si hold time sih v cc = 5 v, figure 10 50 ? ? ns csb setup time cssup v cc = 5 v, figure 10 100 ? ? ns csb high time csh v cc = 5 v, figure 10 200 ? ? ns so enable after csb falling edge (note 12) cstsof v cc = 5 v, figure 10 ? ? 50 ns so disable after csb rising edge (note 12) cstsor v cc = 5 v, figure 10 ? ? 50 ns so rise time sor v cc = 5 v, c load = 40 pf ? ? 25 ns so fall time sof v cc = 5 v, c load = 40 pf ? ? 25 ns so valid time (note 12) sov v cc = 5 v, c load = 40 pf, figure 10 ? ? 50 ns en low valid time enl 10 ? ? s en delay time end v cc = inx = 5 v en going high 50% to out5 ? out8 turning on 50%. ? ? 100 s spi wake up after en rising edge spiwak si = 5 v, csb = 0 v, sclk = 10 mhz, en going high 50% to so going high 50%, figure 9 ? ? 200 s 12. not subject to production testing.
ncv7608 http://onsemi.com 11 csb sclk css up clk h clk l clk sup css up cstsov csb so sov sih so sclk si figure 10. detailed spi timing clk sup cs h cstsof sisup
ncv7608 http://onsemi.com 12 typical performance characteristics figure 11. i(vs) vs. temperature figure 12. r ds(on) vs. temperature figure 13. i(vs) standby current vs. vs at 25 c figure 14. output over current vs. temperature figure 15. r ds(on) vs. vs figure 16. standby output leakage vs. vs 0.0 1.0 2.0 3.0 4.0 5.0 6.0 ? 50 0 50 100 150 200 vs = 3 v, hs vs = 5.5 v, hs vs = 3 v, ls vs = 8 v, hs vs = 5.5 v, ls vs = 8 v, ls r ds(on) ) temperature ( c) 1.380 1.400 1.420 1.440 1.460 1.480 1.500 1.520 1.540 ? 50 0 50 100 150 200 i lim (a) temperature ( c) vs = 16 v, hs vs = 16 v, ls temperature ( c) i(vs) (ma) 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 ? 1.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 0 i(vs) a) vs (v) 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 r ds(on) ) vs (v) ls driver hs driver 2 4 6 8 10 12 ? 2 0 2 4 6 8 10 12 0 5 10 15 20 25 30 35 drain and supply voltage (v) output leakage ( a) ? 40 c 125 c 25 c 150 c 0 5 10 15 15 20 30 25 0 5 10 15 20 30 25 ? 5 0 0.5 1.0 1.5 2.0 2.5 ? 50 0 50 100 150 200 vs = 28 v, v cc = 5.5 v vs = 28 v, v cc = 3.15 v vs = 5.5 v, v cc = 5.25 v vs = 5.5 v, v cc = 3.15 v
ncv7608 http://onsemi.com 13 typical performance characteristics figure 17. i(vcc) vs. temperature figure 18. vs standby current vs. temperature figure 19. open load detect current vs. temperature figure 20. open load detect current vs. vs @ 25 c figure 21. source ? to ? drain voltage body diode figure 22. output clamp vs. temperature ? 500 ? 400 ? 300 ? 200 ? 100 0 100 200 300 0 5 10 15 20 25 30 open load diagnostic current ( a) vs (v) high side low side i(vs) ( a) 16 14 12 10 8 6 4 2 0 ? 2 ? 50 0 50 100 150 200 temperature ( c) vs = 28 v, v cc = 3.15 v vs = 13.2 v, v cc = 3.15 v vs = 28 v, v cc = 5.25 v vs = 13.2 v, v cc = 5.25 v vs = 5.5 v, v cc = 5.25 v vs = 5.5 v, v cc = 3.15 v 300 200 100 0 ? 100 ? 200 ? 300 ? 400 ? 500 open load diagnostic current ( a) temperature ( c) ? 50 0 50 100 150 ls, vs = 28 v ls, vs = 5.5 v hs, vs = 5.5 v hs, vs = 28 v ? 30 ? 20 ? 10 0 10 20 30 40 50 ? 50 0 50 100 150 200 clamp voltage (v) temperature ( c) drain ? to ? source clamp source ? to ? ground clamp v(diode) (v) i(diode) (a) 1.20 1.00 0.60 0.80 0.40 0.20 0.00 0 0.10 0.20 0.30 0.40 ? 40 c 25 c 125 c 150 c temperature ( c) i(vcc) ( a) ? 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 vs = 5.5 v, v cc = 5.25 v ? 50 0 50 100 150 200 vs = 5.5 v, v cc = 3.15 v vs = 28 v, v cc = 5.25 v vs = 28 v, v cc = 3.15 v
ncv7608 http://onsemi.com 14 detailed operating description normal operation power outputs the ncv7608 provides eight independent power transistors with pins d1 ? d8, and s1 ? s8 as drain and source outputs respectively. for high ? side drive configurations (sourcing), the drain pins are connected to the battery supply. in low ? side configurations (sinking), the drain pins are connected to the load. all outputs may be configured as high ? side, low ? side, half ? bridge, or h ? bridge. internal clamping structures are provided to limit transient voltages when switching inductive loads. spi ? interface the device provides a 16 bit spi ? interface. data is imported into the ncv7608 thro ugh the si (serial input) pin. data is exported out of the ncv7608 through the so (serial output) pin. the input ? frame (si) is used to command the output stages and program individual channel open load diagnostics. the response frame (so) provides channel ? specific (1bit / channel) status information and fault information. see table 1 for channel status decoding. words should be composed of 16 bits lsb (least significant bit) transmitted first. figure 23. spi frame csb si sclk so out1 out2 out3 out4 out5 out6 out7 out8 ol1 ol2 ol3 ol4 ol5 ol6 ol7 ol8 tw out1 out2 out3 out4 out5 out6 out7 out8 in5 state in6 state in7 state in8 state n/a n/a vs psm tw csb si sclk so ol7 ol8 n/a vs psm out1 figure 24. spi frame detail
ncv7608 http://onsemi.com 15 table 2. spi input / output input data output data bit number bit description bit status bit number bit description bit status 15 driver 8 open diagnostic enable 0 = disable 15 vs power supply monitoring 0 = no fault 1 = enable 1 = fault 14 driver 7 open diagnostic enable 0 = disable 14 n/a 0 1 = enable 13 driver 6 open diagnostic enable driver 6 open diagnostic enable 0 = disable 13 n/a 0 1 = enable 12 driver 5 open diagnostic enable 0 = disable 12 in8 state (note 13) 0 = (in8 = 0) 1 = enable 1 = (in8 = 1) 11 driver 4 open diagnostic enable 0 = disable 11 in7 state (note 13) 0 = (in7 = 0) 1 = enable 1 = (in7 = 1) 10 driver 3 open diagnostic enable 0 = disable 10 in6 state (note 13) 0 = (in6 = 0) 1 = enable 1 = (in6 = 1) 9 driver 2 open diagnostic enable 0 = disable 9 in5 state (note 13) 0 = (in5 = 0) 1 = enable 1 = (in5 = 1) 8 driver 1 open diagnostic enable 0 = disable 8 driver 8 status 0 = no fault 1 = enable 1 = fault 7 driver 8 enable 0 = disable 7 driver 7 status 0 = no fault 1 = enable 1 = fault 6 driver 7 enable 0 = disable 6 driver 6 status 0 = no fault 1 = enable 1 = fault 5 driver 6 enable 0 = disable 5 driver 5 status 0 = no fault 1 = enable 1 = fault 4 driver 5 enable 0 = disable 4 driver 4 status 0 = no fault 1 = enable 1 = fault 3 driver 4 enable 0 = disable 3 driver 3 status 0 = no fault 1 = enable 1 = fault 2 driver 3 enable 0 = disable 2 driver 2 status 0 = no fault 1 = enable 1 = fault 1 driver 2 enable 0 = disable 1 driver 1 status 0 = no fault 1 = enable 1 = fault 0 driver 1 enable 0 = disable 0 thermal warning (tw) 0 = no fault 1 = enable 1 = fault an output driver (driver status) fault is either open load, over current, or over temperature. 13. when over current or thermal shutdown fault occurs, bits 9 through 12 records the state of inx.
ncv7608 http://onsemi.com 16 spi input driver enable (bits 0 ? 7) a zero turns the driver off. a one turns the driver on. open load diagnostic (bits 8 ? 15) a zero programming bit disables the detection of an open load condition. a one programming bit enables the detection of an open load condition. parallel input (inx) state (bits 9 ? 12) the state of the parallel (pwm) input pins (inx) are mirrored to spi output bits #9 ? 12. when overcurrent or thermal shutdown fault occurs, bits 9 through 12 record the state of inx. this enables the user to distinguish an open load fault from an over current fault when the ncv7608 is operated from two isolated controllers for the spi input and the parallel input. spi output table 3. so driver status information summary (bits 0 ? 8, 15) driver enable open load diagnostic enable so feedback status information reset requirement disabled disabled 0 n/a disabled enabled 0 (no open load) n/a 1 (open load detected) n/a enabled x 0 (no fault) n/a 1 (over current) a valid spi command with the offending driver disabled is re- ceived. 1 (vs power supply fail) any valid spi command and vs within limits 1 (thermal warning) n/a 1 (thermal shutdown) the over temperature goes away and a valid spi frame with the offending driver pair disabled is received. x=don?t care frame detection input word integrity (si) is evaluated by the use of a frame consistency check. the word frame length is compared to an n * 16 bit (where n is an integer) acceptable word length before the data is latched into the input register. this guarantees the proper word length has been imported and allows for daisy chain operation applications. the frame length detector is enabled with the csb falling edge and the sclk rising edge. sclk must be low during the csb rising edge. reference the valid spi frame shown below. csb si sclk frame detection starts after the csb falling edge and the sclk rising edge. internal counter 910 11 12 13 14 15 16 frame detection mode ends with csb rising edge. valid 16 bits shown out1 out2 out3 out4 out5 out6 out7 out8 ol1 ol2 ol3 ol4 ol5 ol6 ol7 ol8 12345678 figure 25. frame detection pwm operation channels 5, 6, 7, and 8 can be controlled via the serial port (spi) or via the respective parallel port input pins (in5 ? in8). the spi information is or?d with the respective parallel input control pins (inx). inx = 1 activates the output stage.
ncv7608 http://onsemi.com 17 inx = 0 deactivates the output stage. special attention should be paid to detection of over current and open load conditions when operated in a pwm mode. these faults are detected in a 100 s (typ) time window. faults will not be detected at higher frequencies if the time period of the input signal does not allow for 100 s detection time. handling of fault conditions table 4. fault summary table fault fault memory driver condition output register clear requirement open load none allowed to turn on n/a over current latched latched off a valid spi command is received with the offending driver disabled thermal warning none allowed to turn/ remain on as long as the device is not in thermal shutdown n/a thermal shutdown latched (note 14) latched off the over temperature goes away and a valid spi frame with the offending driver pair disabled is received. vs power supply fail latched (note 14) allowed to turn on while the voltage is within operating range after any valid spi frame & voltage within operating range 14. latched conditions are cleared in the same manner (via the spi port) during normal operation regardless of the driver turn on command p ath (via a spi command or via a parallel input command). latches are also cleared by cycling the en pin or with a power ? on reset of v cc .
ncv7608 http://onsemi.com 18 start driver on yes open load tfol w csb lo report fault no fault reported on so no yes yes no current limit thermal warning thermal shutdown vs power supply fail tfoc delay delay delay yes yes yes yes over current thermal warning thermal shutdown r vs power supply fail yes yes yes yes no no no no no no no no report fault latch fault fault reported on so w csb lo report fault latch fault yes report fault no fault reported on so fault reported on so fault reported on so report fault latch fault figure 26. fault reporting flow chart fault filters the ncv7608 detects overtemperature, over current, vs power supply and open load faults. faults are reported in the output data fault register. the fault filter timer for over current or open load is 100 s (typ). an over current or open load event must exist for this period of time to be recognized. there are eight fault timers, one dedicated to each driver for use for both over current and open load. thermal warning, thermal shutdown and vs power supply fail each have there own dedicated timers. open load open load conditions are detected in the off mode. see ?off ? mode open load diagnostics? for details. over current the output current is limited in both high ? side and low ? side conf iguration. over current is detected in the turn on mode. high power dissipation during over current can cause overtemperature shutdown. over current is a latched off event. latching off a driver in over current is especially useful in systems utilizing a hierarchical software architecture whereby the microprocessor sends a command (such as turning a device on when a short circuit exists) and then proceeds to other focused microprocessor activity. eliminating an auto retry upon over current fault detection scheme reduces ic stress by reducing the frequency of attempts to turn back on. thermal warning & overtemperature shutdown four independent overtemperature shutdown circuits are featured (one common sensor for each drive pair). channels are sequentially paired together with its own thermal detection circuit as channels 1 and 2, channels 3 and 4, channels 5 and 6, and channels 7 and 8. each thermal detection circuit senses two temperature levels, one to give a thermal warning (145 c typ) (tw, bit = 0), and one to shut the driver pair off (overtemperature) at a higher temperature 30 c above tw (175 c typ). when the thermal detection circuit reaches the temperature point of thermal warning, the output data bit 0 (tw) will be set to a 1, and the outputs will remain on. overtemperature events will be recorded as faults to the offending output driver pair
ncv7608 http://onsemi.com 19 independently of the input state (serial or parallel). overtemperature shutdown is a latched event. since thermal warning precedes an overtemperature shutdown, software polling of this bit will allow for load control and possible prevention of overtemperature shutdown conditions. thermal warning retrieval thermal warning information can be retrieved immediately without performing a complete spi access cycle. figure 27 below displays how this is accomplished. bringing the csb pin from a 1 to a 0 condition immediately displays the information on the output data bit 0, thermal warning, even in the absence of a sclk signal. as the temperature of the ncv7608 changes from a condition from below the thermal warning threshold to above the thermal warning threshold, the state of the so pin changes and this level is available immediately when the csb goes to 0. a 0 on so indicates there is no thermal warning, while a 1 indicates the ic is above the thermal warning threshold. figure 27. accessing thermal warning bit power supply monitoring undervoltage shutdown both supply voltages (v cc and vs) are monitored for undervoltage. when v cc goes below the threshold, all outputs are turned off and the input and output registers are cleared. an undervoltage condition on vs will cause all channels to shut down. the fault bit (bit #15) is latched in the output data register. the channels will return to the commanded status after reaching operational vs levels provided v cc uvlo is not breached. the spi port remains active during vs undervoltage within a valid vcc voltage. drivers are guaranteed to operate with automotive cranking voltages down to 3 v on vs per the undervoltage shutdown thresholds. bit# 15 is cleared with a valid spi frame and vs within the operating limits. overvoltage shutdown vs is continuously monitored for overvoltage conditions. the threshold is set above automotive jump start conditions allowing operation of the ic during jump start. the minimum overvoltage threshold is 32 v. when vs goes above the overvoltage threshold voltage, all outputs are turned off. the fault bit (bit #15) is latched in the output data register. input and output registers maintain all information. the channels will return to the commanded status after reaching operational vs levels provided v cc uvlo is not breached. the spi port remains active during vs overvoltage within a valid vcc voltage. bit #15 is cleared with any valid spi frame and vs within the operating limits. off ? mode open load diagnostics open load diagnostics are performed when the drivers are off (provided the channel is programmed to perform the operation via bits #8 through #15). open load diagnostics are performed by connecting two tracking current sources (idiaghsx and idiaglsx) to the corresponding outputs. to support both operation modes (high ? side and low ? side) and provide minimum delay due to external capacitances, both drain and source pin voltages of the device are monitored to generate the diagnostic information. channel diagnostic information is directed to the output data register. open load diagnostics are disabled during vs undervoltage or overvoltage events or when en is low. figure 28 shows the ncv7608 open load diagnostics principles. figure 29 shows the internal circuitry used with the device set up as a low ? side driver. figure 30 shows the internal circuitry used with the device set up as a high ? side driver.
ncv7608 http://onsemi.com 20 figure 28. open load diagnostic principle figure 29. open load circuitry as low side driver figure 30. open load circuitry as high side driver open load diagnostic performance system design sometimes requires open load diagnostics to be turned off to prevent unintended operation. input bits 8 ? 15 control this function. one application example would be driving led?s. leaving the diagnostic circuitry turned on would result in visible illumination of the led?s because of the currents used in open load detection. open load detection may still be utilized by testing at low time intervals. miscellaneous enable a logic low on en puts the device in a current saving mode. quiescent current (v cc ) with en low is less than 5 a. a logic high on en powers up the device allowing operation through the parallel inputs (in5...in8). an internal pulldown resistor is provided to ensure device turn ? off in the event the enable signal is lost. a low on en will result in a power ? on ? reset to the logic. all outputs will be shut off and all registers reset. loss of ground the ncv7608 output drivers will not be active during a loss of ground condition. no damage to the device will occur during this condition for vs less than or equal to 16 v. diagnostic implementation to provide maximum flexibility in using the device as an h ? bridge driver, a current ratio between the hs and ls diagnostic currents is implemented (the diagnostic source current is always higher in magnitude than the diagnostic
ncv7608 http://onsemi.com 21 sink current). equal diagnostic currents would result in unpredictable results due to process variation. timing information open load open load is reported if open load is enabled and an open load fault exists. open load is not a latched condition and is not reported when drivers are on. to be captured, open load must be present when csb goes low. * spi driver enable bit = 0 and associated inx = 0 ol enabled driver off* ol enabled driver off ol enabled driver off ol enabled driver off ol enabled driver off ol enabled driver on ol disabled driver off csb no fault?fault?no fault fault?no fault?fault no fault so open load exists open load absent ol disabled driver on no fault open load exists open load absent open load exists driver turns on driver turns on no open load exists figure 31. open load timing diagram over current over current is reported if the drivers? over current detection threshold is breached. the driver is latched off after 100 s from the over current detection. to reset the driver status bit for over current, a valid spi frame with enx = 0 is required. this will reset the driver status bit and the driver can be turned back on in the next valid spi frame. driver ondriver ondriver off driver on csb no fault?fault fault no fault so over current detected driver latched off over current condition is removed driver turns on fault is reset inx=0 no over current detected. figure 32. over current timing diagram thermal warning and thermal shutdown thermal warning is reported in bit #0 when the die temperature goes above 145 c (typ) and does not fall below 145 c (typ) ? 30 c hysteresis (typ). thermal warning is only sampled and reported when csb is low. thermal shutdown will turn off the two drivers associated with the thermal sensor when the die temperature is above 175 c (typ). the driver status bit will be latched. the driver status is reset if the die temperature falls below 175 c (typ) ? 30 c (typ) and a valid spi frame with the driver(s) x enable bit = 0. the driver(s) can then be turned on in the next valid spi frame with the driver x enable(s) = 1.
ncv7608 http://onsemi.com 22 driver ondriver ondriver off driver on csb no fault?fault?no fault fault so tw is detected driver continues to run thermal warning condition is removed tw is detected driver continues to be off no tw detected figure 33. thermal warning timing diagram driver ondriver offdriver on csb fault fault?no fault so t<(175 c-30 c) tsd (t > 175 c) driver off driver turns on fault reset figure 34. thermal shutdown timing diagram power supply fail vs overvoltage (ov) or undervoltage (uv) is reported using bit #15 (psm) in the so output data register. this is a latched event. drivers will shut off during vs ov or uv. when coming out of vs ov or uv, the drivers will take on the state determined by the last valid spi frame. the vs power supply monitoring bit (bit #15) will be reset by any valid spi frame.
ncv7608 http://onsemi.com 23 figure 35. power supply fail timing diagram assumes a valid spi frame. 0 200 400 600 800 figure 36. ja vs. copper heat spreader copper heat spreader area (mm 2 ) ja ( c/w) 1.0 oz 0 0.5 1.0 1.5 2.0 2.5 3.0 0 200 400 500 800 figure 37. maximum power vs. copper heat spreader copper heat spreader area (mm 2 ) maximum power (w) 100 300 500 700 170 150 130 110 90 70 50 2.0 oz 2.0 oz 1.0 oz 28 lead soic 36 lead ssop ? ep 28 lead soic 36 lead ssop ? ep 2.0 oz 2.0 oz 1.0 oz 1.0 oz 100 300 600 900 700
ncv7608 http://onsemi.com 24 figure 38. ncv7608 ? 28 lead soic (body 18x7.55x2.55 mm) pcb cu area 650 sq mm pcb thk 2 oz all outputs on time (sec) 100 0.001 0.01 0.0001 0.1 0.00001 10 0.000001 0.01 0.1 1 10 100 figure 39. 4.2x5.8x0.25 mm ? 36 lead ssop ? ep pcb cu area 650 sq mm pcb thk 2 oz all outputs on time (sec) r(t) ( c/w) 1 1000 100 0.001 0.01 0.0001 0.1 0.00001 10 0.000001 0.01 0.1 1 10 100 r(t) ( c/w) 1 1000 single pulse duty cycle = 50% 1% 2% 5% 10% 20% single pulse duty cycle = 50% 1% 2% 5% 10% 20%
ncv7608 http://onsemi.com 25 typical application the drawing below demonstrates the versatility of the ncv7608 in a typical application. in5 in6 in7 in8 csb sclk si so vcc vs d1 s1 d2 s2 d3 s3 d4 s4 d6 s6 d5 s5 d8 s8 d7 s7 gnd ncv7608 en mcu 3.3v ncv8664 vs vs vs vs 320 mh, 70 ohm 320 mh, 70 ohm vs ls relay hs relay 5v ncv7608 supports both 3.3 v and 5 v digital rail 13.2 v mra4003t3 100 nf 10 uf for 5 v 22 uf for 3.3 v 100 nf 13.2v 100 nf ordering information device package shipping ? NCV7608DWR2G soic ? 28 wb (pb ? free) 1000 / tape & reel ncv7608dqr2g ssop36 ? ep (pb ? free) 1500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv7608 http://onsemi.com 26 package dimensions soic ? 28 wb case 751f ? 05 issue h 11.00 28x 0.52 28x 1.30 1.27 dimensions: millimeters 1 pitch soldering footprint* 28 14 15 8x a1 1 15 14 28 b s x m 0.025 y s t m 0.25 y m seating plane a dim min max millimeters a 2.35 2.65 a1 0.13 0.29 b 0.35 0.49 c 0.23 0.32 d 17.80 18.05 e 7.40 7.60 g 1.27 bsc h 10.05 10.55 l 0.41 0.90 m 0 8 l c pin 1 ident d e h 0.10 ? x ? ? y ? g ? t ? m notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold protrusion 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable damber pr5otrusion shall not be 0.13 totatl in excess of b dimension at maximum material condition. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
ncv7608 http://onsemi.com 27 package dimensions case 940ab issue o dim min max millimeters e2 3.90 4.10 a 2.65 a1 --- 0.10 l 0.50 0.90 e 0.50 bsc c 0.23 0.32 h 0.25 0.75 b 0.18 0.36 d2 5.70 5.90 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at mmc. 4. dimension b shall be measured between 0.10 and 0.25 from the tip. 5. dimensions d and e1 do not include mold flash, protrusions or gate burrs. dimensions d and e1 shall be determined at datum h. 6. this chamfer feature is optional. if it is not present, a pin one identifier must be loacated within the indic- ated area. pin 1 reference d e1 0.10 seating plane 36x b e e detail a --- soldering footprint* l l2 gauge detail a e/2 detail b a2 2.35 2.60 e1 7.50 bsc plane seating plane c x c h end view a m 0.25 b t top view side view a-b 0.20 c 118 19 36 a b d detail b 36x a1 a2 c c d2 e2 bottom view 36x d 10.30 bsc e 10.30 bsc m1 5 15 5.90 36x 1.06 36x 0.36 0.50 dimensions: millimeters pitch 4.10 10.76 1 0.25 c s s 4x h a x = a or b h note 6 m1 m 36x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncv7608/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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